Typically, a clocking signal used in a digital core is delivered by an on-chip clock generation unit or frequency synthesizer. The clock generation unit may be a Phase Locked Loop (PLL) device, which could also be implemented in the form of a digital PLL. However, such clocking signals may be a source of electromagnetic interference (EMI) to other portions of a system utilizing the digital core. Undesirable electromagnetic energy may propagate throughout the system, or to the external environment, and cause adverse effects to other susceptible devices.
Electromagnetic compatibility (EMC) requirements in various industries, such as the automotive and consumer electronics industries, for example, put stringent limits on the emission of electromagnetic radiation of electronic devices. Accordingly, spread spectrum clocks have been developed for use in digital cores that spread the electromagnetic energy over a wide frequency spectrum, thereby reducing the magnitude of energy at or near a given frequency. A spread spectrum clock may be produced by modulating the output frequency of a PLL, for example, with a periodic low-frequency pattern (e.g., triangular pattern, sinusoidal pattern, cubic pattern a.k.a. “Hershey-Kiss,” etc.). The periodic low-frequency modulation “spreads” the energy of the clock signal over a wider bandwidth, effectively reducing the peak spectrum electromagnetic emission.
Low frequency up-spread modulation, where the modulation profile is above the nominal frequency of the un-modulated clocking signal, is generally used for safety critical applications, such as automotive applications. In such applications it is important that the digital core delivers a minimum guaranteed frequency to the system, in case any emergency procedure has to be taken automatically by the system. However, when using up-spread modulation, the digital core must be constrained for a higher maximum frequency, with resulting power and area costs. For example, if the nominal (un-modulated) frequency is 300 MHz, and the up-spread spread spectrum has a peak-peak value of 5%, the maximum frequency in the system grows to 315 MHz. The digital core must be constrained to this frequency, leading to higher power and area consumption. Additionally, low frequency up-spread modulation may introduce an accumulation of phase over time, which can lead to problems in the operation of synchronous data interfaces between the digital core and other un-modulated cores.